diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 4b7d569b3464..c40239709c7d 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -237,6 +237,58 @@ static const int rzg2ul_pin_info[] = {
RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
};
+static const int rzfive_pin_info[] = {
+ RZG2L_PIN_INFO(0, 0), RZG2L_PIN_INFO(0, 1), RZG2L_PIN_INFO(0, 2),
+ RZG2L_PIN_INFO(0, 3),
+ RZG2L_PIN_INFO(1, 0), RZG2L_PIN_INFO(1, 1), RZG2L_PIN_INFO(1, 2),
+ RZG2L_PIN_INFO(1, 3), RZG2L_PIN_INFO(1, 4),
+ RZG2L_PIN_INFO(2, 0), RZG2L_PIN_INFO(2, 1), RZG2L_PIN_INFO(2, 2),
+ RZG2L_PIN_INFO(2, 3),
+ RZG2L_PIN_INFO(3, 0), RZG2L_PIN_INFO(3, 1), RZG2L_PIN_INFO(3, 2),
+ RZG2L_PIN_INFO(3, 3),
+ RZG2L_PIN_INFO(4, 0), RZG2L_PIN_INFO(4, 1), RZG2L_PIN_INFO(4, 2),
+ RZG2L_PIN_INFO(4, 3), RZG2L_PIN_INFO(4, 4), RZG2L_PIN_INFO(4, 5),
+ RZG2L_PIN_INFO(5, 0), RZG2L_PIN_INFO(5, 1), RZG2L_PIN_INFO(5, 2),
+ RZG2L_PIN_INFO(5, 3), RZG2L_PIN_INFO(5, 4),
+ RZG2L_PIN_INFO(6, 0), RZG2L_PIN_INFO(6, 1), RZG2L_PIN_INFO(6, 2),
+ RZG2L_PIN_INFO(6, 3), RZG2L_PIN_INFO(6, 4),
+ RZG2L_PIN_INFO(7, 0), RZG2L_PIN_INFO(7, 1), RZG2L_PIN_INFO(7, 2),
+ RZG2L_PIN_INFO(7, 3), RZG2L_PIN_INFO(7, 4),
+ RZG2L_PIN_INFO(8, 0), RZG2L_PIN_INFO(8, 1), RZG2L_PIN_INFO(8, 2),
+ RZG2L_PIN_INFO(8, 3), RZG2L_PIN_INFO(8, 4),
+ RZG2L_PIN_INFO(9, 0), RZG2L_PIN_INFO(9, 1), RZG2L_PIN_INFO(9, 2),
+ RZG2L_PIN_INFO(9, 3),
+ RZG2L_PIN_INFO(10, 0), RZG2L_PIN_INFO(10, 1), RZG2L_PIN_INFO(10, 2),
+ RZG2L_PIN_INFO(10, 3), RZG2L_PIN_INFO(10, 4),
+ RZG2L_PIN_INFO(11, 0), RZG2L_PIN_INFO(11, 1), RZG2L_PIN_INFO(11, 2),
+ RZG2L_PIN_INFO(11, 3),
+ RZG2L_PIN_INFO(12, 0), RZG2L_PIN_INFO(12, 1),
+ RZG2L_PIN_INFO(13, 0), RZG2L_PIN_INFO(13, 1), RZG2L_PIN_INFO(13, 2),
+ RZG2L_PIN_INFO(13, 3), RZG2L_PIN_INFO(13, 4),
+ RZG2L_PIN_INFO(14, 0), RZG2L_PIN_INFO(14, 1), RZG2L_PIN_INFO(14, 2),
+ RZG2L_PIN_INFO(15, 0), RZG2L_PIN_INFO(15, 1), RZG2L_PIN_INFO(15, 2),
+ RZG2L_PIN_INFO(15, 3),
+ RZG2L_PIN_INFO(16, 0), RZG2L_PIN_INFO(16, 1),
+ RZG2L_PIN_INFO(17, 0), RZG2L_PIN_INFO(17, 1), RZG2L_PIN_INFO(17, 2),
+ RZG2L_PIN_INFO(17, 3),
+ RZG2L_PIN_INFO(18, 0), RZG2L_PIN_INFO(18, 1), RZG2L_PIN_INFO(18, 2),
+ RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
+ RZG2L_PIN_INFO(19, 0), RZG2L_PIN_INFO(19, 1), RZG2L_PIN_INFO(19, 2),
+ RZG2L_PIN_INFO(20, 0), RZG2L_PIN_INFO(20, 1), RZG2L_PIN_INFO(20, 2),
+ RZG2L_PIN_INFO(20, 3), RZG2L_PIN_INFO(20, 4), RZG2L_PIN_INFO(20, 5),
+ RZG2L_PIN_INFO(20, 6), RZG2L_PIN_INFO(20, 7),
+ RZG2L_PIN_INFO(21, 0), RZG2L_PIN_INFO(21, 1),
+ RZG2L_PIN_INFO(22, 0), RZG2L_PIN_INFO(22, 1), RZG2L_PIN_INFO(22, 2),
+ RZG2L_PIN_INFO(22, 3),
+ RZG2L_PIN_INFO(23, 0), RZG2L_PIN_INFO(23, 1), RZG2L_PIN_INFO(23, 2),
+ RZG2L_PIN_INFO(23, 3), RZG2L_PIN_INFO(23, 4), RZG2L_PIN_INFO(23, 5),
+ RZG2L_PIN_INFO(24, 0), RZG2L_PIN_INFO(24, 1), RZG2L_PIN_INFO(24, 2),
+ RZG2L_PIN_INFO(24, 3), RZG2L_PIN_INFO(24, 4), RZG2L_PIN_INFO(24, 5),
+ RZG2L_PIN_INFO(25, 0), RZG2L_PIN_INFO(25, 1),
+ RZG2L_PIN_INFO(28, 0), RZG2L_PIN_INFO(28, 1), RZG2L_PIN_INFO(28, 2),
+ RZG2L_PIN_INFO(28, 3), RZG2L_PIN_INFO(28, 4), RZG2L_PIN_INFO(28, 5),
+};
+
struct rzg2l_dedicated_configs {
const char *name;
u32 config;
@@ -1512,6 +1564,36 @@ static const u32 r9a07g043_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
};
+static const u32 r9a07g043f_gpio_configs[] = {
+ RZG2L_GPIO_PORT_PACK(3, 0x06, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(7, 0x07, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x08, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(4, 0x09, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(6, 0x0a, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(6, 0x0b, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x0c, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
+};
+
static struct {
struct rzg2l_dedicated_configs common[35];
struct rzg2l_dedicated_configs rzg2l_pins[7];
@@ -1598,6 +1680,22 @@ static struct {
}
};
+static struct rzg2l_dedicated_configs rzfive_dedicated_pins[10] = {
+ { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
+ (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
+ { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
+ (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
+ { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
+ (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
+ { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
+ { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
+ { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
+ { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
+ { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
+ { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
+ { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
+};
+
static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
{
struct device_node *np = pctrl->dev->of_node;
@@ -1880,12 +1978,12 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
static struct rzg2l_pinctrl_data r9a07g043f_data = {
.port_pins = rzg2l_gpio_names,
- .port_pin_configs = r9a07g043_gpio_configs,
- .dedicated_pins = rzg2l_dedicated_pins.common,
- .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
- .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
- .pin_info = rzg2ul_pin_info,
- .ngpioints = ARRAY_SIZE(rzg2ul_pin_info),
+ .port_pin_configs = r9a07g043f_gpio_configs,
+ .dedicated_pins = rzfive_dedicated_pins,
+ .n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT,
+ .n_dedicated_pins = ARRAY_SIZE(rzfive_dedicated_pins),
+ .pin_info = rzfive_pin_info,
+ .ngpioints = ARRAY_SIZE(rzfive_pin_info),
.irq_mask = true,
};
