[root@nixos:~]# dtc -I fs /sys/firmware/devicetree/base
...
/dts-v1/;
/ {
#address-cells = <0x02>;
model = "Bananapi BPI-R64";
#size-cells = <0x02>;
interrupt-parent = <0x01>;
compatible = "bananapi,bpi-r64\0mediatek,mt7622";
i2c@11009000 {
clock-div = <0x10>;
pinctrl-names = "default";
#address-cells = <0x01>;
pinctrl-0 = <0x1a>;
clock-names = "main\0dma";
interrupts = <0x00 0x56 0x08>;
clocks = <0x15 0x15 0x15 0x0a>;
#size-cells = <0x00>;
compatible = "mediatek,mt7622-i2c";
status = "okay";
reg = <0x00 0x11009000 0x00 0x90 0x00 0x11000200 0x00 0x80>;
};
serial@11019000 {
clock-names = "baud\0bus";
interrupts = <0x00 0x59 0x08>;
clocks = <0x11 0x40 0x15 0x11>;
compatible = "mediatek,mt7622-uart\0mediatek,mt6577-uart";
status = "disabled";
reg = <0x00 0x11019000 0x00 0x400>;
};
pcie@1a140000 {
power-domains = <0x1e 0x01>;
pinctrl-names = "default";
#address-cells = <0x03>;
bus-range = <0x00 0xff>;
pinctrl-0 = <0x31 0x32>;
clock-names = "sys_ck0\0sys_ck1\0ahb_ck0\0ahb_ck1\0aux_ck0\0aux_ck1\0axi_ck0\0axi_ck1\0obff_ck0\0obff_ck1\0pipe_ck0\0pipe_ck1";
reg-names = "subsys\0port0\0port1";
interrupts = <0x00 0xe4 0x08 0x00 0xe5 0x08>;
clocks = <0x30 0x0a 0x30 0x04 0x30 0x08 0x30 0x08 0x30 0x06 0x30 0x00 0x30 0x09 0x30 0x03 0x30 0x07 0x30 0x01 0x30 0x0b 0x30 0x05>;
#size-cells = <0x02>;
device_type = "pci";
compatible = "mediatek,mt7622-pcie";
ranges = <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x10000000>;
status = "okay";
reg = <0x00 0x1a140000 0x00 0x1000 0x00 0x1a143000 0x00 0x1000 0x00 0x1a145000 0x00 0x1000>;
pcie@1,0 {
#address-cells = <0x03>;
interrupt-map = <0x00 0x00 0x00 0x01 0x34 0x00 0x00 0x00 0x00 0x02 0x34 0x01 0x00 0x00 0x00 0x03 0x34 0x02 0x00 0x00 0x00 0x04 0x34 0x03>;
#size-cells = <0x02>;
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
ranges;
#interrupt-cells = <0x01>;
status = "okay";
reg = <0x800 0x00 0x00 0x00 0x00>;
interrupt-controller {
#address-cells = <0x00>;
#interrupt-cells = <0x01>;
phandle = <0x34>;
interrupt-controller;
};
};
pcie@0,0 {
#address-cells = <0x03>;
interrupt-map = <0x00 0x00 0x00 0x01 0x33 0x00 0x00 0x00 0x00 0x02 0x33 0x01 0x00 0x00 0x00 0x03 0x33 0x02 0x00 0x00 0x00 0x04 0x33 0x03>;
#size-cells = <0x02>;
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
ranges;
#interrupt-cells = <0x01>;
status = "okay";
reg = <0x00 0x00 0x00 0x00 0x00>;
interrupt-controller {
#address-cells = <0x00>;
#interrupt-cells = <0x01>;
phandle = <0x33>;
interrupt-controller;
};
};
};
interrupt-controller@10200620 {
interrupt-parent = <0x0e>;
compatible = "mediatek,mt7622-sysirq\0mediatek,mt6577-sysirq";
#interrupt-cells = <0x03>;
reg = <0x00 0x10200620 0x00 0x20>;
phandle = <0x01>;
interrupt-controller;
};
regulator-3p3v {
regulator-max-microvolt = <0x325aa0>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x325aa0>;
regulator-name = "fixed-3.3V";
compatible = "regulator-fixed";
phandle = <0x27>;
};
oscillator {
clock-output-names = "clkxtal";
#clock-cells = <0x00>;
clock-frequency = <0x17d7840>;
compatible = "fixed-clock";
phandle = <0x1f>;
};
nfi@1100d000 {
pinctrl-names = "default";
#address-cells = <0x01>;
pinctrl-0 = <0x21>;
clock-names = "nfi_clk\0pad_clk";
interrupts = <0x00 0x60 0x08>;
clocks = <0x15 0x1a 0x15 0x19>;
#size-cells = <0x00>;
compatible = "mediatek,mt7622-nfc";
status = "disabled";
ecc-engine = <0x20>;
reg = <0x00 0x1100d000 0x00 0x1000>;
};
serial@11005000 {
clock-names = "baud\0bus";
interrupts = <0x00 0x5e 0x08>;
clocks = <0x11 0x40 0x15 0x10>;
compatible = "mediatek,mt7622-uart\0mediatek,mt6577-uart";
status = "disabled";
reg = <0x00 0x11005000 0x00 0x400>;
};
mmc@11230000 {
pinctrl-names = "default\0state_uhs";
pinctrl-0 = <0x25>;
clock-names = "source\0hclk";
vqmmc-supply = <0x28>;
assigned-clocks = <0x11 0x44>;
assigned-clock-parents = <0x11 0x2e>;
mmc-hs200-1_8v;
bus-width = <0x08>;
non-removable;
resets = <0x15 0x13>;
interrupts = <0x00 0x4f 0x08>;
clocks = <0x15 0x0b 0x11 0x43>;
vmmc-supply = <0x27>;
compatible = "mediatek,mt7622-mmc";
pinctrl-1 = <0x26>;
status = "okay";
reg = <0x00 0x11230000 0x00 0x1000>;
max-frequency = <0x2faf080>;
cap-mmc-highspeed;
reset-names = "hrst";
};
serial@11002000 {
pinctrl-names = "default";
pinctrl-0 = <0x16>;
clock-names = "baud\0bus";
interrupts = <0x00 0x5b 0x08>;
clocks = <0x11 0x40 0x15 0x0d>;
compatible = "mediatek,mt7622-uart\0mediatek,mt6577-uart";
status = "okay";
reg = <0x00 0x11002000 0x00 0x400>;
};
spi@11016000 {
pinctrl-names = "default";
#address-cells = <0x01>;
pinctrl-0 = <0x23>;
clock-names = "parent-clk\0sel-clk\0spi-clk";
interrupts = <0x00 0x7a 0x08>;
clocks = <0x11 0x19 0x11 0x42 0x15 0x16>;
#size-cells = <0x00>;
compatible = "mediatek,mt7622-spi";
status = "disabled";
reg = <0x00 0x11016000 0x00 0x100>;
};
syscon@1b000000 {
#reset-cells = <0x01>;
#clock-cells = <0x01>;
compatible = "mediatek,mt7622-ethsys\0syscon";
reg = <0x00 0x1b000000 0x00 0x1000>;
phandle = <0x36>;
};
ssusbsys@1a000000 {
#reset-cells = <0x01>;
#clock-cells = <0x01>;
compatible = "mediatek,mt7622-ssusbsys\0syscon";
reg = <0x00 0x1a000000 0x00 0x1000>;
phandle = <0x2b>;
};
regulator-5v {
regulator-max-microvolt = <0x4c4b40>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x4c4b40>;
regulator-name = "fixed-5V";
compatible = "regulator-fixed";
phandle = <0x2f>;
};
thermal-zones {
cpu-thermal {
polling-delay = <0x3e8>;
polling-delay-passive = <0x3e8>;
thermal-sensors = <0x0a 0x00>;
trips {
cpu-crit {
temperature = <0x1a1f8>;
hysteresis = <0x7d0>;
type = "critical";
};
cpu-passive {
temperature = <0xb798>;
hysteresis = <0x7d0>;
type = "passive";
phandle = <0x0b>;
};
cpu-hot {
temperature = <0x153d8>;
hysteresis = <0x7d0>;
type = "hot";
phandle = <0x0d>;
};
cpu-active {
temperature = <0x105b8>;
hysteresis = <0x7d0>;
type = "active";
phandle = <0x0c>;
};
};
cooling-maps {
map2 {
trip = <0x0d>;
cooling-device = <0x08 0xffffffff 0xffffffff 0x09 0xffffffff 0xffffffff>;
};
map0 {
trip = <0x0b>;
cooling-device = <0x08 0xffffffff 0xffffffff 0x09 0xffffffff 0xffffffff>;
};
map1 {
trip = <0x0c>;
cooling-device = <0x08 0xffffffff 0xffffffff 0x09 0xffffffff 0xffffffff>;
};
};
};
};
pwm@11006000 {
pinctrl-names = "default";
pinctrl-0 = <0x18>;
clock-names = "top\0main\0pwm1\0pwm2\0pwm3\0pwm4\0pwm5\0pwm6";
interrupts = <0x00 0x4d 0x08>;
clocks = <0x11 0x3c 0x15 0x09 0x15 0x02 0x15 0x03 0x15 0x04 0x15 0x05 0x15 0x06 0x15 0x07>;
compatible = "mediatek,mt7622-pwm";
status = "okay";
reg = <0x00 0x11006000 0x00 0x1000>;
};
i2c@11008000 {
clock-div = <0x10>;
pinctrl-names = "default";
#address-cells = <0x01>;
pinctrl-0 = <0x19>;
clock-names = "main\0dma";
interrupts = <0x00 0x55 0x08>;
clocks = <0x15 0x14 0x15 0x0a>;
#size-cells = <0x00>;
compatible = "mediatek,mt7622-i2c";
status = "okay";
reg = <0x00 0x11008000 0x00 0x90 0x00 0x11000180 0x00 0x80>;
};
apmixedsys@10209000 {
#clock-cells = <0x01>;
compatible = "mediatek,mt7622-apmixedsys\0syscon";
reg = <0x00 0x10209000 0x00 0x1000>;
phandle = <0x03>;
};
rtc@10212800 {
clock-names = "rtc";
interrupts = <0x00 0x81 0x08>;
clocks = <0x11 0x0f>;
compatible = "mediatek,mt7622-rtc\0mediatek,soc-rtc";
reg = <0x00 0x10212800 0x00 0x200>;
};
infracfg@10000000 {
#reset-cells = <0x01>;
#clock-cells = <0x01>;
compatible = "mediatek,mt7622-infracfg\0syscon";
reg = <0x00 0x10000000 0x00 0x1000>;
phandle = <0x02>;
};
topckgen@10210000 {
#clock-cells = <0x01>;
compatible = "mediatek,mt7622-topckgen\0syscon";
reg = <0x00 0x10210000 0x00 0x1000>;
phandle = <0x11>;
};
mmc@11240000 {
pinctrl-names = "default\0state_uhs";
pinctrl-0 = <0x29>;
clock-names = "source\0hclk";
cap-sd-highspeed;
vqmmc-supply = <0x27>;
assigned-clocks = <0x11 0x45>;
assigned-clock-parents = <0x11 0x2e>;
bus-width = <0x04>;
resets = <0x15 0x14>;
interrupts = <0x00 0x50 0x08>;
clocks = <0x15 0x0c 0x11 0x38>;
vmmc-supply = <0x27>;
compatible = "mediatek,mt7622-mmc";
pinctrl-1 = <0x2a>;
status = "okay";
reg = <0x00 0x11240000 0x00 0x1000>;
max-frequency = <0x2faf080>;
reset-names = "hrst";
cd-gpios = <0x13 0x51 0x01>;
r_smpl = <0x01>;
};
leds {
compatible = "gpio-leds";
green {
label = "bpi-r64:pio:green";
default-state = "off";
gpios = <0x13 0x59 0x00>;
};
red {
label = "bpi-r64:pio:red";
default-state = "off";
gpios = <0x13 0x58 0x00>;
};
};
psci {
method = "smc";
compatible = "arm,psci-0.2";
};
efuse@10206000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "mediatek,mt7622-efuse\0mediatek,efuse";
reg = <0x00 0x10206000 0x00 0x1000>;
calib@198 {
reg = <0x198 0x0c>;
phandle = <0x1d>;
};
};
spi@1100a000 {
pinctrl-names = "default";
#address-cells = <0x01>;
pinctrl-0 = <0x1b>;
clock-names = "parent-clk\0sel-clk\0spi-clk";
interrupts = <0x00 0x76 0x08>;
clocks = <0x11 0x19 0x11 0x41 0x15 0x18>;
#size-cells = <0x00>;
compatible = "mediatek,mt7622-spi";
status = "okay";
reg = <0x00 0x1100a000 0x00 0x100>;
};
serial@11004000 {
pinctrl-names = "default";
pinctrl-0 = <0x17>;
clock-names = "baud\0bus";
interrupts = <0x00 0x5d 0x08>;
clocks = <0x11 0x40 0x15 0x0f>;
compatible = "mediatek,mt7622-uart\0mediatek,mt6577-uart";
status = "disabled";
reg = <0x00 0x11004000 0x00 0x400>;
};
cci@10390000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "arm,cci-400";
ranges = <0x00 0x00 0x10390000 0x10000>;
reg = <0x00 0x10390000 0x00 0x1000>;
slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
reg = <0x4000 0x1000>;
interface-type = "ace";
};
slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
reg = <0x1000 0x1000>;
interface-type = "ace-lite";
};
pmu@9000 {
interrupts = <0x00 0x3a 0x04 0x00 0x3b 0x04 0x00 0x3c 0x04 0x00 0x3d 0x04 0x00 0x3e 0x04>;
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
};
slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
reg = <0x5000 0x1000>;
interface-type = "ace";
phandle = <0x05>;
};
};
opp-table {
opp-shared;
compatible = "operating-points-v2";
phandle = <0x04>;
opp-437500000 {
opp-microvolt = <0xf4240>;
opp-hz = <0x00 0x1a13b860>;
};
opp-1262500000 {
opp-microvolt = <0x1312d0>;
opp-hz = <0x00 0x4b4038a0>;
};
opp-300000000 {
opp-microvolt = <0xe7ef0>;
opp-hz = <0x00 0x1c9c380>;
};
opp-1025000000 {
opp-microvolt = <0x118c30>;
opp-hz = <0x00 0x3d184240>;
};
opp-812500000 {
opp-microvolt = <0x10c8e0>;
opp-hz = <0x00 0x306dc420>;
};
opp-1137500000 {
opp-microvolt = <0x124f80>;
opp-hz = <0x00 0x43ccdf60>;
};
opp-600000000 {
opp-microvolt = <0x100590>;
opp-hz = <0x00 0x23c34600>;
};
opp-1350000000 {
opp-microvolt = <0x13fd30>;
opp-hz = <0x00 0x50775d80>;
};
};
gpio-keys {
compatible = "gpio-keys";
wps {
label = "wps";
linux,code = <0x211>;
gpios = <0x13 0x66 0x00>;
};
factory {
label = "factory";
linux,code = <0x100>;
gpios = <0x13 0x00 0x00>;
};
};
dma-controller@1b007000 {
power-domains = <0x1e 0x00>;
clock-names = "hsdma";
interrupts = <0x00 0xdb 0x08>;
clocks = <0x36 0x00>;
compatible = "mediatek,mt7622-hsdma";
reg = <0x00 0x1b007000 0x00 0x1000>;
#dma-cells = <0x01>;
};
pwrap@10001000 {
pinctrl-names = "default";
pinctrl-0 = <0x10>;
clock-names = "spi\0wrap";
reg-names = "pwrap";
resets = <0x02 0x07>;
interrupts = <0x00 0xa3 0x04>;
clocks = <0x02 0x05 0x0f>;
compatible = "mediatek,mt7622-pwrap";
status = "okay";
reg = <0x00 0x10001000 0x00 0x250>;
reset-names = "pwrap";
regulators {
compatible = "mediatek,mt6380-regulator";
ldo-vm {
regulator-max-microvolt = <0x155cc0>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x100590>;
regulator-name = "vm";
regulator-ramp-delay = <0x00>;
phandle = <0x07>;
};
ldo-vphy {
regulator-max-microvolt = <0x1b7740>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x1b7740>;
regulator-name = "vphy";
regulator-ramp-delay = <0x00>;
};
ldo-vt {
regulator-max-microvolt = <0x325aa0>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x2191c0>;
regulator-name = "vt";
regulator-ramp-delay = <0x00>;
};
ldo-va {
regulator-max-microvolt = <0x325aa0>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x2191c0>;
regulator-name = "va";
regulator-ramp-delay = <0x00>;
};
buck-vcore {
regulator-max-microvolt = <0x154456>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x927c0>;
regulator-name = "vcore";
regulator-ramp-delay = <0x186a>;
};
buck-vrf {
regulator-max-microvolt = <0x180858>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x124f80>;
regulator-name = "vrf";
regulator-ramp-delay = <0x00>;
};
buck-vcore1 {
regulator-max-microvolt = <0x154456>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x927c0>;
regulator-name = "vcore1";
regulator-ramp-delay = <0x186a>;
phandle = <0x06>;
};
ldo-vddr {
regulator-max-microvolt = <0x1c1380>;
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <0x12ebc0>;
regulator-name = "vddr";
regulator-ramp-delay = <0x00>;
};
};
};
pericfg@10002000 {
#reset-cells = <0x01>;
#clock-cells = <0x01>;
compatible = "mediatek,mt7622-pericfg\0syscon";
reg = <0x00 0x10002000 0x00 0x1000>;
phandle = <0x15>;
};
ecc@1100e000 {
clock-names = "nfiecc_clk";
interrupts = <0x00 0x5f 0x08>;
clocks = <0x15 0x1b>;
compatible = "mediatek,mt7622-ecc";
status = "disabled";
reg = <0x00 0x1100e000 0x00 0x1000>;
phandle = <0x20>;
};
watchdog@10212000 {
pinctrl-names = "default";
pinctrl-0 = <0x14>;
compatible = "mediatek,mt7622-wdt\0mediatek,mt6589-wdt";
status = "okay";
reg = <0x00 0x10212000 0x00 0x800>;
};
regulator-1p8v {
regulator-max-microvolt = <0x1b7740>;
regulator-always-on;
regulator-min-microvolt = <0x1b7740>;
regulator-name = "fixed-1.8V";
compatible = "regulator-fixed";
phandle = <0x28>;
};
t-phy@1a243000 {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "mediatek,mt7622-tphy\0mediatek,generic-tphy-v1";
ranges;
status = "disable";
sata-phy@1a243000 {
clock-names = "ref";
clocks = <0x11 0x37>;
#phy-cells = <0x01>;
reg = <0x00 0x1a243000 0x00 0x100>;
phandle = <0x35>;
};
};
timer {
interrupts = <0x01 0x0d 0x304 0x01 0x0e 0x304 0x01 0x0b 0x304 0x01 0x0a 0x304>;
interrupt-parent = <0x0e>;
compatible = "arm,armv8-timer";
};
serial@1100c000 {
reg-io-width = <0x04>;
clock-names = "main";
interrupts = <0x00 0x5a 0x08>;
clocks = <0x15 0x12>;
compatible = "mediatek,mt7622-btif\0mediatek,mtk-btif";
status = "okay";
reg = <0x00 0x1100c000 0x00 0x1000>;
reg-shift = <0x02>;
bluetooth {
power-domains = <0x1e 0x03>;
clock-names = "ref";
clocks = <0x1f>;
compatible = "mediatek,mt7622-bluetooth";
};
};
aliases {
serial0 = "/serial@11002000";
};
i2c@11007000 {
clock-div = <0x10>;
#address-cells = <0x01>;
clock-names = "main\0dma";
interrupts = <0x00 0x54 0x08>;
clocks = <0x15 0x13 0x15 0x0a>;
#size-cells = <0x00>;
compatible = "mediatek,mt7622-i2c";
status = "disabled";
reg = <0x00 0x11007000 0x00 0x90 0x00 0x11000100 0x00 0x80>;
};
rng@1020f000 {
clock-names = "rng";
clocks = <0x02 0x06>;
compatible = "mediatek,mt7622-rng\0mediatek,mt7623-rng";
reg = <0x00 0x1020f000 0x00 0x1000>;
};
wmac@18000000 {
power-domains = <0x1e 0x03>;
interrupts = <0x00 0xd3 0x08>;
compatible = "mediatek,mt7622-wmac";
status = "okay";
reg = <0x00 0x18000000 0x00 0x100000>;
mediatek,infracfg = <0x02>;
};
interrupt-controller@10300000 {
interrupt-parent = <0x0e>;
compatible = "arm,gic-400";
#interrupt-cells = <0x03>;
reg = <0x00 0x10310000 0x00 0x1000 0x00 0x10320000 0x00 0x1000 0x00 0x10340000 0x00 0x2000 0x00 0x10360000 0x00 0x2000>;
phandle = <0x0e>;
interrupt-controller;
};
chosen {
linux,initrd-end = <0x00 0x7f7f9243>;
bootargs = "init=/nix/store/xzaicsw37kq6qwkrrn3y8xk3d03zs806-nixos-system-nixos-21.11pre332842.8afc4e54366/init console=ttyS0,115200n1 loglevel=4";
linux,initrd-start = <0x00 0x7e572000>;
stdout-path = "serial0:115200n8";
};
t-phy@1a0c4000 {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "mediatek,mt7622-tphy\0mediatek,generic-tphy-v1";
ranges;
status = "okay";
reg = <0x00 0x1a0c4000 0x00 0x700>;
usb-phy@1a0c4900 {
clock-names = "ref";
clocks = <0x1f>;
#phy-cells = <0x01>;
reg = <0x00 0x1a0c4900 0x00 0x700>;
phandle = <0x2d>;
};
usb-phy@1a0c4800 {
clock-names = "ref";
clocks = <0x2b 0x01>;
#phy-cells = <0x01>;
reg = <0x00 0x1a0c4800 0x00 0x100>;
phandle = <0x2c>;
};
usb-phy@1a0c5000 {
clock-names = "ref";
clocks = <0x2b 0x00>;
#phy-cells = <0x01>;
reg = <0x00 0x1a0c5000 0x00 0x100>;
phandle = <0x2e>;
};
};
dummy40m {
#clock-cells = <0x00>;
clock-frequency = <0x2625a00>;
compatible = "fixed-clock";
phandle = <0x0f>;
};
sata@1a200000 {
power-domains = <0x1e 0x01>;
phy-names = "sata-phy";
clock-names = "ahb\0axi\0asic\0rbc\0pm";
resets = <0x30 0x0f 0x30 0x0d 0x30 0x0c>;
interrupts = <0x00 0xe9 0x04>;
clocks = <0x30 0x0c 0x30 0x0d 0x30 0x0e 0x30 0x0f 0x30 0x10>;
compatible = "mediatek,mt7622-ahci\0mediatek,mtk-ahci";
status = "disable";
interrupt-names = "hostc";
phys = <0x35 0x01>;
mediatek,phy-mode = <0x30>;
reg = <0x00 0x1a200000 0x00 0x1100>;
ports-implemented = <0x01>;
reset-names = "axi\0sw\0reg";
};
ethernet@1b100000 {
power-domains = <0x1e 0x00>;
#address-cells = <0x01>;
clock-names = "ethif\0esw\0gp0\0gp1\0gp2\0sgmii_tx250m\0sgmii_rx250m\0sgmii_cdr_ref\0sgmii_cdr_fb\0sgmii_ck\0eth2pll";
interrupts = <0x00 0xdf 0x08 0x00 0xe0 0x08 0x00 0xe1 0x08>;
clocks = <0x11 0x3b 0x36 0x01 0x36 0x04 0x36 0x03 0x36 0x02 0x37 0x00 0x37 0x01 0x37 0x02 0x37 0x03 0x11 0x2f 0x03 0x04>;
mediatek,sgmiisys = <0x37>;
#size-cells = <0x00>;
mediatek,ethsys = <0x36>;
compatible = "mediatek,mt7622-eth\0mediatek,mt2701-eth\0syscon";
status = "okay";
reg = <0x00 0x1b100000 0x00 0x20000>;
mac@0 {
phy-mode = "2500base-x";
compatible = "mediatek,eth-mac";
reg = <0x00>;
phandle = <0x38>;
fixed-link {
full-duplex;
speed = <0x9c4>;
pause;
};
};
mdio-bus {
#address-cells = <0x01>;
#size-cells = <0x00>;
switch@0 {
reset-gpios = <0x13 0x36 0x00>;
compatible = "mediatek,mt7531";
reg = <0x00>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
label = "wan";
reg = <0x00>;
};
port@3 {
label = "lan2";
reg = <0x03>;
};
port@1 {
label = "lan0";
reg = <0x01>;
};
port@6 {
phy-mode = "2500base-x";
label = "cpu";
reg = <0x06>;
ethernet = <0x38>;
fixed-link {
full-duplex;
speed = <0x9c4>;
pause;
};
};
port@4 {
label = "lan3";
reg = <0x04>;
};
port@2 {
label = "lan1";
reg = <0x02>;
};
};
};
};
mac@1 {
phy-mode = "rgmii";
compatible = "mediatek,eth-mac";
reg = <0x01>;
fixed-link {
full-duplex;
speed = <0x3e8>;
pause;
};
};
};
serial@11003000 {
clock-names = "baud\0bus";
interrupts = <0x00 0x5c 0x08>;
clocks = <0x11 0x40 0x15 0x0e>;
compatible = "mediatek,mt7622-uart\0mediatek,mt6577-uart";
status = "disabled";
reg = <0x00 0x11003000 0x00 0x400>;
};
cir@10009000 {
pinctrl-names = "default";
pinctrl-0 = <0x12>;
clock-names = "clk\0bus";
interrupts = <0x00 0xaf 0x08>;
clocks = <0x02 0x03 0x11 0x38>;
compatible = "mediatek,mt7622-cir";
status = "okay";
reg = <0x00 0x10009000 0x00 0x1000>;
};
spi@11014000 {
pinctrl-names = "default";
#address-cells = <0x01>;
pinctrl-0 = <0x22>;
clock-names = "spi\0sf";
clocks = <0x15 0x1c 0x11 0x3f>;
#size-cells = <0x00>;
compatible = "mediatek,mt7622-nor\0mediatek,mt8173-nor";
status = "disabled";
reg = <0x00 0x11014000 0x00 0xe0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x00>;
};
};
usb@1a0c0000 {
power-domains = <0x1e 0x02>;
clock-names = "sys_ck\0ref_ck\0mcu_ck\0dma_ck";
reg-names = "mac\0ippc";
vusb33-supply = <0x27>;
interrupts = <0x00 0xe8 0x08>;
clocks = <0x2b 0x03 0x2b 0x02 0x2b 0x04 0x2b 0x05>;
vbus-supply = <0x2f>;
compatible = "mediatek,mt7622-xhci\0mediatek,mtk-xhci";
status = "okay";
phys = <0x2c 0x03 0x2d 0x04 0x2e 0x03>;
reg = <0x00 0x1a0c0000 0x00 0x1000 0x00 0x1a0c4700 0x00 0x100>;
};
adc@11001000 {
clock-names = "main";
clocks = <0x15 0x17>;
#io-channel-cells = <0x01>;
compatible = "mediatek,mt7622-auxadc";
reg = <0x00 0x11001000 0x00 0x1000>;
phandle = <0x1c>;
};
pciesys@1a100800 {
#reset-cells = <0x01>;
#clock-cells = <0x01>;
compatible = "mediatek,mt7622-pciesys\0syscon";
reg = <0x00 0x1a100800 0x00 0x1000>;
phandle = <0x30>;
};
thermal@1100b000 {
nvmem-cells = <0x1d>;
clock-names = "therm\0auxadc";
resets = <0x15 0x10>;
interrupts = <0x00 0x4e 0x08>;
clocks = <0x15 0x01 0x15 0x17>;
mediatek,apmixedsys = <0x03>;
#thermal-sensor-cells = <0x01>;
compatible = "mediatek,mt7622-thermal";
nvmem-cell-names = "calibration-data";
reg = <0x00 0x1100b000 0x00 0x1000>;
phandle = <0x0a>;
reset-names = "therm";
mediatek,auxadc = <0x1c>;
};
pmu {
interrupt-affinity = <0x08 0x09>;
interrupts = <0x00 0x08 0x08 0x00 0x09 0x08>;
compatible = "arm,cortex-a53-pmu";
};
cpus {
#address-cells = <0x02>;
#size-cells = <0x00>;
cpu@1 {
proc-supply = <0x06>;
clock-names = "cpu\0intermediate";
clocks = <0x02 0x00 0x03 0x09>;
clock-frequency = "M|m";
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x00 0x01>;
enable-method = "psci";
phandle = <0x09>;
cci-control-port = <0x05>;
operating-points-v2 = <0x04>;
sram-supply = <0x07>;
#cooling-cells = <0x02>;
};
cpu@0 {
proc-supply = <0x06>;
clock-names = "cpu\0intermediate";
clocks = <0x02 0x00 0x03 0x09>;
clock-frequency = "M|m";
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x00 0x00>;
enable-method = "psci";
phandle = <0x08>;
cci-control-port = <0x05>;
operating-points-v2 = <0x04>;
sram-supply = <0x07>;
#cooling-cells = <0x02>;
};
};
clock-controller@11220000 {
#clock-cells = <0x01>;
compatible = "mediatek,mt7622-audsys\0syscon";
reg = <0x00 0x11220000 0x00 0x2000>;
phandle = <0x24>;
audio-controller {
clock-names = "infra_sys_audio_clk\0top_audio_mux1_sel\0top_audio_mux2_sel\0top_audio_a1sys_hp\0top_audio_a2sys_hp\0i2s0_src_sel\0i2s1_src_sel\0i2s2_src_sel\0i2s3_src_sel\0i2s0_src_div\0i2s1_src_div\0i2s2_src_div\0i2s3_src_div\0i2s0_mclk_en\0i2s1_mclk_en\0i2s2_mclk_en\0i2s3_mclk_en\0i2so0_hop_ck\0i2so1_hop_ck\0i2so2_hop_ck\0i2so3_hop_ck\0i2si0_hop_ck\0i2si1_hop_ck\0i2si2_hop_ck\0i2si3_hop_ck\0asrc0_out_ck\0asrc1_out_ck\0asrc2_out_ck\0asrc3_out_ck\0audio_afe_pd\0audio_afe_conn_pd\0audio_a1sys_pd\0audio_a2sys_pd";
assigned-clocks = <0x11 0x46 0x11 0x47 0x11 0x63 0x11 0x64>;
assigned-clock-parents = <0x11 0x31 0x11 0x32>;
assigned-clock-rates = <0x00 0x00 0x2ee0000 0x2b11000>;
interrupts = <0x00 0x90 0x08 0x00 0x91 0x08>;
clocks = <0x02 0x02 0x11 0x50 0x11 0x51 0x11 0x6b 0x11 0x6c 0x11 0x59 0x11 0x5a 0x11 0x5b 0x11 0x5c 0x11 0x5f 0x11 0x60 0x11 0x61 0x11 0x62 0x11 0x67 0x11 0x68 0x11 0x69 0x11 0x6a 0x24 0x08 0x24 0x09 0x24 0x0a 0x24 0x0b 0x24 0x04 0x24 0x05 0x24 0x06 0x24 0x07 0x24 0x0e 0x24 0x0f 0x24 0x27 0x24 0x28 0x24 0x00 0x24 0x2e 0x24 0x11 0x24 0x12>;
compatible = "mediatek,mt7622-audio";
interrupt-names = "afe\0asys";
};
};
sgmiisys@1b128000 {
#clock-cells = <0x01>;
compatible = "mediatek,mt7622-sgmiisys\0syscon";
reg = <0x00 0x1b128000 0x00 0x3000>;
phandle = <0x37>;
};
reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
secmon@43000000 {
reg = <0x00 0x43000000 0x00 0x30000>;
no-map;
};
};
power-controller@10006000 {
infracfg = <0x02>;
clock-names = "hif_sel";
interrupts = <0x00 0xa5 0x08 0x00 0xa6 0x08 0x00 0xa7 0x08 0x00 0xa8 0x08>;
clocks = <0x11 0x4d>;
#power-domain-cells = <0x01>;
compatible = "mediatek,mt7622-scpsys\0syscon";
reg = <0x00 0x10006000 0x00 0x1000>;
phandle = <0x1e>;
};
pinctrl@10211000 {
reg-names = "base\0eint";
gpio-controller;
interrupts = <0x00 0x99 0x04>;
interrupt-parent = <0x0e>;
compatible = "mediatek,mt7622-pinctrl";
#interrupt-cells = <0x02>;
reg = <0x00 0x10211000 0x00 0x1000 0x00 0x10005000 0x00 0x1000>;
phandle = <0x13>;
#gpio-cells = <0x02>;
gpio-ranges = <0x13 0x00 0x00 0x67>;
interrupt-controller;
watchdog-pins {
phandle = <0x14>;
mux {
function = "watchdog";
groups = "watchdog";
};
};
i2s1-pins {
mux {
function = "i2s";
groups = "i2s_out_mclk_bclk_ws\0i2s1_in_data\0i2s1_out_data";
};
conf {
pins = "I2S1_IN\0I2S1_OUT\0I2S_BCLK\0I2S_WS\0I2S_MCLK";
drive-strength = <0x0c>;
bias-pull-down;
};
};
spi-nor-pins {
phandle = <0x22>;
mux {
function = "flash";
groups = "spi_nor";
};
};
asm_sel {
gpio-hog;
output-high;
gpios = <0x5a 0x00>;
};
irtx-pins {
mux {
function = "ir";
groups = "ir_1_tx";
};
};
emmc-pins-default {
phandle = <0x25>;
conf-cmd-dat {
pins = "NDL0\0NDL1\0NDL2\0NDL3\0NDL4\0NDL5\0NDL6\0NDL7\0NRB";
bias-pull-up;
input-enable;
};
conf-clk {
pins = "NCLE";
bias-pull-down;
};
mux {
function = "emmc\0emmc_rst";
groups = "emmc";
};
};
emmc-pins-uhs {
phandle = <0x26>;
conf-cmd-dat {
pins = "NDL0\0NDL1\0NDL2\0NDL3\0NDL4\0NDL5\0NDL6\0NDL7\0NRB";
drive-strength = <0x04>;
bias-pull-up;
input-enable;
};
conf-clk {
pins = "NCLE";
drive-strength = <0x04>;
bias-pull-down;
};
mux {
function = "emmc";
groups = "emmc";
};
};
serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
sd0-pins-uhs {
phandle = <0x2a>;
conf-clk {
pins = "I2S3_OUT";
bias-pull-down;
};
mux {
function = "sd";
groups = "sd_0";
};
conf-cmd-data {
pins = "I2S2_OUT\0I2S4_IN\0I2S3_IN\0I2S2_IN\0I2S4_OUT";
bias-pull-up;
input-enable;
};
};
i2c2-pins {
phandle = <0x1a>;
mux {
function = "i2c";
groups = "i2c2_0";
};
};
i2c1-pins {
phandle = <0x19>;
mux {
function = "i2c";
groups = "i2c1_0";
};
};
irrx-pins {
phandle = <0x12>;
mux {
function = "ir";
groups = "ir_1_rx";
};
};
pmic-bus-pins {
phandle = <0x10>;
mux {
function = "pmic";
groups = "pmic_bus";
};
};
wled-pins {
mux {
function = "led";
groups = "wled";
};
};
uart2-pins {
phandle = <0x17>;
mux {
function = "uart";
groups = "uart2_1_tx_rx";
};
};
sd0-pins-default {
phandle = <0x29>;
conf-clk {
pins = "I2S3_OUT";
drive-strength = <0x0c>;
bias-pull-down;
};
conf-cd {
pins = "TXD3";
bias-pull-up;
};
mux {
function = "sd";
groups = "sd_0";
};
conf-cmd-data {
pins = "I2S2_OUT\0I2S4_IN\0I2S3_IN\0I2S2_IN\0I2S4_OUT";
drive-strength = <0x08>;
bias-pull-up;
input-enable;
};
};
spic1-pins {
phandle = <0x23>;
mux {
function = "spi";
groups = "spic1_0";
};
};
eth-pins {
mux {
function = "eth";
groups = "mdc_mdio\0rgmii_via_gmac2";
};
};
pcie1-pins {
phandle = <0x32>;
mux {
function = "pcie";
groups = "pcie1_pad_perst\0pcie1_0_waken\0pcie1_0_clkreq";
};
};
pwm-pins {
phandle = <0x18>;
mux {
function = "pwm";
groups = "pwm_ch1_0\0pwm_ch2_0\0pwm_ch3_2\0pwm_ch4_1\0pwm_ch5_0\0pwm_ch6_0";
};
};
parallel-nand-pins {
phandle = <0x21>;
mux {
function = "flash";
groups = "par_nand";
};
};
spic0-pins {
phandle = <0x1b>;
mux {
function = "spi";
groups = "spic0_0";
};
};
pcie0-pins {
phandle = <0x31>;
mux {
function = "pcie";
groups = "pcie0_pad_perst\0pcie0_1_waken\0pcie0_1_clkreq";
};
};
uart0-pins {
phandle = <0x16>;
mux {
function = "uart";
groups = "uart0_0_tx_rx";
};
};
};
memory {
device_type = "memory";
reg = <0x00 0x40000000 0x00 0x40000000>;
};
};