d/g/r>
d/g/r>
d/g/r>
d/g/r>
d/g/r>h
download to 0x80005EF0
Ymodem:
CCCCCr>CC
checksum:0x00018AAC
crc32:0xFE6FD2BC, len:0x000005EC
d/g/r>s
98007078
00000000 98007078 = 0x00000000
d/g/r>
d/g/r>
d/g/r>
d/g/r>s
98007058
01500000 98007058 = 0x01500000
d/g/r>
d/g/r>
d/g/r>
d/g/r>d
download to 0x01500000
Ymodem:
CCCCCCC
checksum:0x066D8526
crc32:0xC4932F05, len:0x0013CD80
d/g/r>
d/g/r>
d/g/r>
d/g/r>
d/g/r>g
jump to 0x01500000
32b
flash_type: eMMC
begin:
emmc : PLL_EMMC1 = 0x00000003
emmc : dummy_buffer = 0x00200000, dummy_512B = 0x00200008
switch frequency to 0x00000046
frequency divider is 0x00000080
switch frequency to 0x00000046
frequency divider is 0x00000004
switch to SDR 8 bit
switch bus width to 0x00000008 bits success
-------->disable dcache
**********for NON_SECURE_BOOT
*******************************************
hwsetting: block 0x00000100, size 0x00000680
read hwsetting back: block 0x00000100, size 0x00000680
*******************************************
write bootcode: block 0x00000104, size 0x0006D920
read back bootcode: block 0x00000104, size 0x0006D920
*******************************************
write bootcode64: byte offset 0x069F0000, block 0x00034F80, size 0x00026360
read back bootcode 64: block 0x00034F80, size 0x00026360
*******************************************
write fsbl,fsbl_sig: block 0x00000471, fsbl size 0x00010B00, fsbl_sig_size 0x00000020
read back data(fsbl/fsbl_sig): block 0x00000471, fsbl size 0x00010B00, fsbl_sig_size 0x00000020
*******************************************
write fsbl_os,fsbl_os_sig: block 0x000004F7, fsbl_os size 0x00067480, fsbl_os_sig_size 0x00000020
read back data(fsbl_os/fsbl_os_sig): block 0x000004F7, fsbl_os size 0x00067480, fsbl_os_sig_size 0x00000020
*******************************************
write bl31,bl31_sig: block 0x00000832, bl31 size 0x00005040, bl31_sig_size 0x00000020
read back data(bl31/bl31_sig): block 0x00000832, bl31 size 0x00005040, bl31_sig_size 0x00000020
*******************************************
write extern_param: block 0x0000007C, size 0x800
read back extern_parm: block 0x0000007C, size 0x00000800
Finish
reset...
C1:80000000
C2
?
C3hswitch frequency to 0x00000046
frequency divider is 0x00000080
switch frequency to 0x00000046
frequency divider is 0x00000004
switch to SDR 8 bit
switch bus width to 0x00000008 bits success
hwsetting size: 000005EC
C4
f
5-5
Goto FSBL: 0x10100000
<=============================================>
fsbl_main: sys_secure_type = 0x0000BEEE
fsbl_main: sys_boot_type = 0x00000002
fsbl_main: sys_boot_enc0ÿ-B”B
======================================
======================================
1295 hw setting.
.config transform to binary.
--------------------------
1295 hw setting.
.config transform to binary.
--------------------------
Transferring HW setting file
1295 hw setting ...
ready to upload hw setting via ymodem
Sending file via ymodem
send header..
wait return header ack
send 1st done
retry
send all done
send end body
wait return end ack
sendy done
hwstting - scan keyword..
hw setting upload successful
--------------------------
enter flash write.
-- flash write start --
-- burn dvrboot.bin start --
ready to upload bootcode via ymodem
Sending file via ymodem
send header..
wait return header ack
send 1st done
retry
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send all done
send end body
wait return end ack
sendy done
scan keyword finish
finish
whole procedure is done